Programmable logic devices (PLDs), such as field programmable gate arrays (FPGAs) or complex programmable logic devices (CPLDs), may be configured to provide user-defined features. In this regard, PLDs typically include logic blocks that are used to perform various logic operations. The configuration of the logic blocks and their interconnections are specified by configuration data programmed into configuration memory of the PLD. To prepare the configuration data, software may be used to identify individual segmented wires that are connected together within the PLD to provide longer wires for interconnecting the logic blocks.
However, conventional approaches used to identify connected segmented wires are often inefficient. In one approach, software is used to search for segmented wires of a PLD on a case-by-case basis for each logic block to be connected. For example, if a first segmented wire connected to a first logic block is found, then adjacent areas of the PLD are searched to find an additional segmented wire connected to the first segmented wire. The two segmented wires may be referenced together as a new wire, and additional segmented wires may be searched and added to the new wire until a set of segmented wires between the first logic block and a second logic block can be determined and referenced together as a new wire.
Unfortunately, in the above approach, the process of searching and identifying segmented wires must be repeated for each interconnection between logic blocks of the PLD. In addition, as each additional segmented wire is found, wire information (e.g., wire position, wire graphical information, and other details) must be created, updated, and/or deleted. As a result, this approach can become cumbersome and time-intensive as each new wire is repeatedly updated to include additional segmented wires, and previously identified new wires are added to other new wires and deleted. Moreover, as PLDs grow in size (for example, at a linear rate), the time to search for and identify segmented wires also increases (for example, at a quadratic rate).
As a result, there is a need for an improved approach to the identification of segmented wires to facilitate the interconnection of PLD logic blocks. In particular, there is a need for such an approach that permits large wires comprised of smaller segmented wires to be easily identified.